LTC4240IGN#TRPBF【PDF 15/28 页】IC CTRLR HOTSWAP CPCI I2C 28SSOP

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LTC4240

4240f

Table 3 shows the definition for each data bit. PWRGD,

FAULT, RESETIN, and RESETOUT external pins can be

monitored. PRSNT1# and PRSNT2# are PCI signals that

provide information on the power requirements of the

board. Refer to PCI local bus specifications for a detailed

description. FAULTCODE1 and FAULTCODE0 are two in-

ternal binary encoded signals that, along with FAULT,

indicate which of the four supplies generated a fault. Note

that the FAULTCODE signals are valid only when FAULT

has been asserted low. See Table 4 for description.

Status LED

The main function of the LED is to alert the user when it is

permissible to physically extract the board. The LED

output of the LTC4240 is an open drain N-channel device

capable of sinking 10mA from an externally connected

LED. This LED lights up when RESETOUT

(LOCAL_PCI_RST#) is asserted. Upon application of Early

Power, the long 5V pins will power up the LTC4240 and

light up the Status LED. It will remain on until PWRGD

(HEALTHY#) is asserted and RESETIN (PCI_RST#) is de-

asserted, and the board enters normal operation. Note that

this LED can also be turned on via the I

C 2-wire interface.

CPCI Connection Pin Sequence

The staggered length of the CPCI male connector pins

ensures that all power supplies are physically connected

APPLICATIO S I FOR ATIO

Table 3. STATUS Byte Definitions

Logic state of the PRSNT2# pin

Logic state of the PRSNT1# pin

Logic state of the PWRGD pin

Logic state of the RESETOUT pin

Logic state of the RESETIN pin

FAULTCODE1 (see Table 4)

FAULTCODE0 (see Table 4)

Logic state of the FAULT pin

Table 4. FAULTCODE Encoding Description for Receive Byte

FAULTCODE0 FAULTCODE1

FAULT

Supply Causing Fault

12V

EEIN

None

SCL

STOP

SDA

START

ACK

R/WR=1

ADDR 4 ADDR 3 ADDR 2 ADDR 1 ADDR 0

ADDRESS BYTE

DATA BYTE

4240 F03

Figure 3. Receive Byte Protocol

to the LTC4240 before back-end power is allowed to ramp

(BD_SEL# asserted low). The long pins, which include 5V,

3.3V, V(I/O) and GND mate first. The short pins, which

includes BD_SEL# (OFF/ON), mate last. At least one long

5V power pin must be connected to the LTC4240 in order

for the PRECHARGE voltage to be available during Early

Power. The external components connected to the

precharge pin require long 3.3V.

The following is a typical hot plug sequence:

1. ESD clips make contact.

2. Long power and ground pins make contact and Early

Power is established (see Early Power section). The 1V

PRECHARGE voltage becomes valid at this stage. Power

is applied to the pull-up resistors connected to FAULT,

PWRGD and OFF/ON pins. The status LED is lit, indicat-

ing that the plug-in board is in the process of being

connected (LOCAL_PCI_RST# is asserted). All power

switches are off.

3. Medium length pins make contact. There are six 5V and

eight 3.3V medium length power pins, bringing the 5V

total to 8 pins and the 3.3V total to 10 pins. The

maximum DC current for the 3.3V and 5V supplies is

10A and 8A, respectively. The I

C command latch is

initialized to allow seamless CPCI Hot Swap operation.

The LTC4240 can be used as a Hot Swap controller

without ever establishing I

C communication. Both

FAULT and PWRGD continue to be pulled up high at this

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